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Espressif Systems /ESP32-S2 /APB_SARADC /CTRL2

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Interpret as CTRL2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MEAS_NUM_LIMIT)MEAS_NUM_LIMIT 0MAX_MEAS_NUM0 (SAR1_INV)SAR1_INV 0 (SAR2_INV)SAR2_INV 0 (TIMER_SEL)TIMER_SEL 0TIMER_TARGET0 (TIMER_EN)TIMER_EN

Description

DIG ADC common configuration

Fields

MEAS_NUM_LIMIT

Enable limit times of SAR ADC sample.
MAX_MEAS_NUM

Set maximum conversion number.
SAR1_INV

1: data to DIG ADC1 CTRL is inverted, otherwise not.
SAR2_INV

1: data to DIG ADC2 CTRL is inverted, otherwise not.
TIMER_SEL

1: select saradc timer 0: i2s_ws trigger
TIMER_TARGET

Set SAR ADC timer target.
TIMER_EN

Enable SAR ADC timer trigger.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd